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ASAHI KASEI
[AK4358]
AK4358
192kHz 24-Bit 8ch DAC with DSD Input
GENERAL DESCRIPTION The AK4358 is eight channels 24bit DAC corresponding to digital audio system. Using AKM's advanced multi bit architecture for its modulator the AK4358 delivers a wide dynamic range while preserving linearity for improved THD+N performance. The AK4358 has full differential SCF outputs, removing the need for AC coupling capacitors and increasing performance for systems with excessive clock jitter. The AK4358 accepts 192kHz PCM data and 1-Bit DSD data, ideal for a wide range of applications including DVD-Audio and SACD. FEATURES Sampling Rate Ranging from 8kHz to 192kHz 24Bit 8 times Digital Filter with Slow roll-off option THD+N: -94dB DR, S/N: 112dB High Tolerance to Clock Jitter Low Distortion Differential Output DSD Data input available Digital De-emphasis for 32, 44.1 & 48kHz sampling Zero Detect function Channel Independent Digital Attenuator with soft-transition (3 Speed mode) Soft Mute 3-wire Serial and I2C Bus P I/F for mode setting I/F format: MSB justified, LSB justified (16bit, 20bit, 24bit), I2S, TDM or DSD Master clock: 256fs, 384fs, 512fs or 768fs (PCM Normal Speed Mode) 128fs, 192fs, 256fs or 384fs (PCM Double Speed Mode) 128fs or 192fs (PCM Quad Speed Mode) 512fs or 768fs (DSD Mode) Power Supply: 4.75 to 5.25V 48pin LQFP Package
DZF LOUT1+ LOUT1ROUT1+ ROUT1LOUT2+ LOUT2ROUT2+ ROUT2LOUT3+ LOUT3ROUT3+ ROUT3LOUT4+ LOUT4ROUT4+ ROUT4-
SCF
DAC
DATT
Audio I/F
SCF
DAC
DATT PCM
SCF
DAC
DATT Control Register
MCLK LRCK BICK SDTI1 SDTI2 SDTI3 SDTI4
SCF
DAC
DATT
3-wire or I2C DCLK DSDL1 DSDR1 DSDL2 DSDR2 DSDL3 DSDR3 DSDL4 DSDR4
SCF
DAC
DATT
SCF SCF
DAC DAC
DATT DSD DATT
SCF
DAC
DATT
AK4358
MS0203-E-00 -1-
2003/02
ASAHI KASEI
[AK4358]
Ordering Guide
AK4358VQ AKD4358 -40 +85C 48LQFP Evaluation Board for AK4358
Pin Layout
ROUT1+
ROUT2+
ROUT3+
LOUT2+
LOUT3+
LOUT4+ 38
ROUT1-
ROUT3-
ROUT2-
LOUT2-
LOUT3-
45
48
44
47
46
43
42
40
41
39
37 36 35 34 33
LOUT4-
LOUT1LOUT1+ DZF3 DZF2 DZF1 CAD0 ACKSN PDN BICK MCLK DVDD DVSS
1 2 3 4 5 6 7 8 9 10 11 12 15 20 17 18 21 13 14 16 19 22 23 24 Top View
AVSS AVDD VREFH ROUT4+ ROUT4DIF0 DSDR3 DSDL3 DSDR2 DSDL2 DSDR1 DSDL1
AK4358VQ
32 31 30 29 28 27 26 25
CSN/CAD1
CDTI/SDA
CCLK/SCL
MS0203-E-00 -2-
DSDR4
SDTI4
SDTI1
SDTI2
SDTI3
DSDL4
DCLK
LRCK
I2C
2003/02
ASAHI KASEI
[AK4358]
Compatibility with AK4357
1. Function & Performance Functions # of channels DR 48kHz/96kHz TDM I2C DSDM control Input channel of DZF pin AK4357 6 106dB Not available Not available Pin/Register Fixed AK4358 8 112dB Available Available Register Programmable
2. Pin Configuration Pin # 3 4 5 7 12 13 18 19 20 21 22 23 24 32 33 37 38 3. Register Addr 00H 01H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH Bit D5 D6 D7 D7 D7 D7 D7 D7 D7, D6 AK4357 DZFM 0 ATT7 ATT7 ATT7 ATT7 ATT7 ATT7 0, 0 Not available Not available Not available Not available Not available AK4358 0 PW4 ATTE ATTE ATTE ATTE ATTE ATTE TDM1, TDM0 LOUT4 ATT Control ROUT4 ATT Control DZF1 control DZF2 control DZF3 control AK4357 DZFL1 DZFR1 DZF23 CAD1 NC DVSS SMUTE CCLK CDTI CSN DSDM DCLK NC DIF1 DIF2 AVSS AVSS AK4358 DZF3 DZF2 DZF1 ACKSN DVSS SDTI4 I2C CCLK/SCL CDTI/SDA CSN/CAD1 DCLK DSDL4 DSDR4 ROUT4ROUT4+ LOUT4LOUT4-
MS0203-E-00 -3-
2003/02
ASAHI KASEI
[AK4358]
PIN/FUNCTION
No. 1 2 3 4 5 6 7 8 Pin Name LOUT1LOUT1+ DZF3 DZF2 DZF1 CAD0 ACKSN PDN I/O O O O O O I I I Function DAC1 Lch Negative Analog Output Pin DAC1 Lch Positive Analog Output Pin Zero Input Detect 3 Pin Zero Input Detect 2 Pin Zero Input Detect 1 Pin Chip Address 0 Pin Auto Setting Mode Disable Pin (Pull-down Pin) "L": Auto Setting Mode, "H": Manual Setting Mode Power-Down Mode Pin When at "L", the AK4358 is in the power-down mode and is held in reset. The AK4358 should always be reset upon power-up. Audio Serial Data Clock Pin Master Clock Input Pin An external TTL clock should be input on this pin. Digital Power Supply Pin, +4.75+5.25V Digital Ground Pin DAC4 Audio Serial Data Input Pin DAC1 Audio Serial Data Input Pin DAC2 Audio Serial Data Input Pin DAC3 Audio Serial Data Input Pin L/R Clock Pin Control Mode Select Pin "L": 3-wire Serial, "H": I2C Bus Control Data Clock Pin I2C = "L": CCLK (3-wire Serial), I2C = "H": SCL (I2C Bus) Control Data Input Pin I2C = "L": CDTI (3-wire Serial), I2C = "H": SDA (I2C Bus) Chip Select Pin I2C = "L": CSN (3-wire Serial), I2C = "H": CAD1 (I2C Bus) DSD Clock Pin DAC4 DSD Lch Data Input Pin DAC4 DSD Rch Data Input Pin DAC1 DSD Lch Data Input Pin DAC1 DSD Rch Data Input Pin DAC2DSD Lch Data Input Pin DAC2 DSD Rch Data Input Pin DAC3 DSD Lch Data Input Pin DAC3 DSD Rch Data Input Pin Audio Data Interface Format 0 Pin DAC4 Rch Negative Analog Output Pin DAC4 Rch Positive Analog Output Pin Positive Voltage Reference Input Pin Analog Power Supply Pin, +4.75+5.25V Analog Ground Pin DAC4 Lch Negative Analog Output Pin DAC4 Lch Positive Analog Output Pin DAC3 Rch Negative Analog Output Pin DAC3 Rch Positive Analog Output Pin DAC3 Lch Negative Analog Output Pin DAC3 Lch Positive Analog Output Pin DAC2 Rch Negative Analog Output Pin DAC2 Rch Positive Analog Output Pin DAC2 Lch Negative Analog Output Pin
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
BICK MCLK DVDD DVSS SDTI4 SDTI1 SDTI2 SDTI3 LRCK I2C CCLK/SCL CDTI/SDA CSN/CAD1 DCLK DSDL4 DSDR4 DSDL1 DSDR1 DSDL2 DSDR2 DSDL3 DSDR3 DIF0 ROUT4ROUT4+ VREFH AVDD AVSS LOUT4LOUT4+ ROUT3ROUT3+ LOUT3LOUT3+ ROUT2ROUT2+ LOUT2-
I I I I I I I I I I/O I I I I I I I I I I I O O I O O O O O O O O O
MS0203-E-00 -4-
2003/02
ASAHI KASEI
[AK4358]
46 LOUT2+ O DAC2 Lch Positive Analog Output Pin 47 ROUT1O DAC1 Rch Negative Analog Output Pin 48 ROUT1+ O DAC1 Rch Positive Analog Output Pin Note: All input pins except pull-down pin should not be left floating.
ABSOLUTE MAXIMUM RATINGS (AVSS, DVSS=0V; Note 1) Parameter Symbol Min Power Supplies Analog AVDD -0.3 Digital DVDD -0.3 |AVSS-DVSS| (Note 2) GND Input Current (any pins except for supplies) IIN Analog Input Voltage VINA -0.3 Digital Input Voltage VIND -0.3 Ambient Operating Temperature Ta -40 Storage Temperature Tstg -65
Note 1. All voltages with respect to ground. Note 2. AVSS and DVSS must be connected to the same analog ground plane.
Max 6.0 6.0 0.3 10 AVDD+0.3 DVDD+0.3 85 150
Units V V V mA V V C C
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS (AVSS, DVSS=0V; Note 1) Parameter Symbol Min Typ Power Supplies Analog AVDD 4.75 5.0 (Note 3) Digital DVDD 4.75 5.0 Voltage Reference VREF AVDD-0.5 Note 3. The power up sequence between AVDD and DVDD is not critical. *AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
Max 5.25 5.25 AVDD
Units V V V
MS0203-E-00 -5-
2003/02
ASAHI KASEI
[AK4358]
ANALOG CHARACTERISTICS (Ta=25C; AVDD, DVDD=5V; VREFH=AVDD; fs=44.1kHz; BICK=64fs; Signal Frequency=1kHz; 24bit Input Data; Measurement frequency=20Hz 20kHz; RL 2k; unless otherwise specified) Parameter Min Typ Max Units Resolution 24 Bits (Note 4) Dynamic Characteristics THD+N fs=44.1kHz 0dBFS -94 -86 dB BW=20kHz -60dBFS -48 dB fs=96kHz 0dBFS -92 -84 dB BW=40kHz -60dBFS -45 dB fs=192kHz 0dBFS -92 dB BW=40kHz -60dBFS -45 dB Dynamic Range (-60dBFS with A-weighted) (Note 5) 102 112 dB S/N (A-weighted) (Note 6) 102 112 dB Interchannel Isolation (1kHz) 90 100 dB Interchannel Gain Mismatch 0.2 0.5 dB DC Accuracy Gain Drift 100 ppm/C Output Voltage (Note 7) Vpp 2.35 2.5 2.65 Load Resistance (Note 8) 2 k Power Supplies Power Supply Current (AVDD+DVDD) mA 70 56 Normal Operation (PDN = "H", fs96kHz) (Note 9) mA 85 62 Normal Operation (PDN = "H", fs=192kHz) (Note 10) A 100 10 Power-Down Mode (PDN = "L") (Note 11)
Note 4. Measured by Audio Precision System Two. Refer to the evaluation board manual. Note 5. 100dB at 16bit data. Note 6. S/N does not depend on input bit length. Note 7. Full scale voltage (0dB). Output voltage scales with the voltage of VREFH pin. AOUT (typ. @0dB) = (AOUT+)-(AOUT-) = 2.5VppxVREFH/5.0 Note 8. For AC-load. 4k for DC-load Note 9 AVDD=40mA(Typ), DVDD=12mA(Typ)@44.1kHz&5V, 16mA(Typ)@96kHz&5V Note 10 AVDD=40mA(Typ), DVDD=22mA(Typ)@192kHz&5V Note 11. All digital inputs including clock pins (MCLK, BICK and LRCK) are held DVDD or DVSS.
MS0203-E-00 -6-
2003/02
ASAHI KASEI
[AK4358]
SHARP ROLL-OFF FILTER CHARACTERISTICS (Ta = 25C; AVDD, DVDD = 4.75 5.25V; fs = 44.1kHz; DEM = OFF; SLOW = "0"; PCM Mode) Parameter Symbol Min Typ Max Digital filter PB 0 20.0 Passband 0.05dB (Note 12) 22.05 -6.0dB Stopband (Note 12) SB 24.1 Passband Ripple PR 0.02 Stopband Attenuation SA 54 Group Delay (Note 13) GD 19.1 Digital Filter + SCF Frequency Response 20.0kHz Fs=44.1kHz FR 0.2 40.0kHz Fs=96kHz FR 0.3 80.0kHz Fs=192kHz FR +0/-0.6
Units kHz kHz kHz dB dB 1/fs dB dB dB
Note 12. The passband and stopband frequencies scale with fs(system sampling rate). For example, PB=0.4535xfs (@0.05dB), SB=0.546xfs. Note 13. The calculating delay time which occurred by digital filtering. This time is from setting the 16/24bit data of both channels to input register to the output of analog signal.
SLOW ROLL-OFF FILTER CHARACTERISTICS (Ta = 25C; AVDD, DVDD = 4.75~5.25V; fs = 44.1kHz; DEM = OFF; SLOW = "1"; PCM Mode)
Parameter Digital Filter Passband 0.04dB -3.0dB (Note 14) (Note 14) PB SB PR SA GD FR FR FR 0 39.2 72 18.2 8.1 0.005 19.1 +0/-5 +0/-4 +0/-5 kHz kHz kHz dB dB 1/fs dB dB dB Symbol Min Typ Max Units
Stopband Passband Ripple Stopband Attenuation Group Delay Digital Filter + SCF Frequency Response
(Note 13) 20.0kHz 40.0kHz 80.0kHz fs=44.kHz fs=96kHz fs=192kHz
Note 14. The passband and stopband frequencies scale with fs. For example, PB = 0.185xfs (@0.04dB), SB = 0.888xfs.
DC CHARACTERISTICS (Ta = 25C; AVDD, DVDD = 4.75 5.25V) Parameter Symbol Min High-Level Input Voltage VIH 2.2 Low-Level Input Voltage VIL High-Level Output Voltage (Iout = -80A) VOH DVDD-0.4 Low-Level Output Voltage (Iout = 80A) VOL Input Leakage Current (Note 15) Iin Note 15. ACKSN pin has internal pull-down devices, nominally 100k.
Typ -
Max 0.8 0.4 10
Units V V V V A
MS0203-E-00 -7-
2003/02
ASAHI KASEI
[AK4358]
SWITCHING CHARACTERISTICS (Ta = 25C; AVDD, DVDD = 4.75 5.25V; CL = 20pF) Parameter Symbol Min fCLK 2.048 Master Clock Frequency Duty Cycle dCLK 40 LRCK Frequency
Normal Mode (TDM0= "L", TDM1= "L") Normal Speed Mode Double Speed Mode Quad Speed Mode Duty Cycle TDM256 mode (TDM0= "H", TDM1= "L") Normal Speed Mode High time Low time TDM128 mode (TDM0= "H", TDM1= "H") Normal Speed Mode Double Speed Mode High time Low time PCM Audio Interface Timing BICK Period BICK Pulse Width Low Pulse Width High BICK "" to LRCK Edge (Note 16) LRCK Edge to BICK "" (Note 16) SDTI Hold Time SDTI Setup Time DSD Audio Interface Timing DCLK Period DCLK Pulse Width Low Pulse Width High DCLK Edge to DSDL/R (Note 17) Control Interface Timing (3-wire Serial mode): CCLK Period CCLK Pulse Width Low Pulse Width High CDTI Setup Time CDTI Hold Time CSN High Time CSN "" to CCLK "" CCLK "" to CSN "" Control Interface Timing (I2C Bus mode): SCL Clock Frequency Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low Time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling (Note 18) SDA Setup Time from SCL Rising Rise Time of Both SDA and SCL Lines Fall Time of Both SDA and SCL Lines Setup Time for Stop Condition Pulse Width of Spike Noise Suppressed by Input Filter fsn fsd fsq Duty fsn tLRH tLRL fsn fsd tLRH tLRL tBCK tBCKL tBCKH tBLR tLRB tSDH tSDS tDCK tDCKL tDCKH tDDD tCCK tCCKL tCCKH tCDS tCDH tCSW tCSS tCSH fSCL tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO tSP 8 60 120 45 32 1/256fs 1/256fs 32 60 1/128fs 1/128fs 81 30 30 20 20 10 10 1/64fs 160 160 -20 200 80 80 40 40 150 50 50 4.7 4.0 4.7 4.0 4.7 0 0.25 4.0 0
Typ 11.2896
Max 36.864 60
Units MHz %
48 96 192 55 48
kHz kHz kHz % kHz ns ns kHz kHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
48 96
20
100 1.0 0.3 50
kHz s s s s s s s s s s ns
MS0203-E-00 -8-
2003/02
ASAHI KASEI
[AK4358]
Parameter Reset Timing PDN Pulse Width
Symbol (Note 19) tPD
Min 150
Typ
Max
Units ns
Note 16. BICK rising edge must not occur at the same time as LRCK edge. Note 17. DSD data transmitting device must meet this time. Note 18. Data must be held for sufficient time to bridge the 300 ns transition time of SCL. Note 19. The AK4358 can be reset by bringing PDN= "L". Note 20. I2C is a registered trademark of Philips Semiconductors.
Purchase of Asahi Kasei Microsystems Co., Ltd I2C components conveys a license under the Philips I2C patent to use the components in the I2C system, provided the system conform to the I2C specifications defined by Philips.
MS0203-E-00 -9-
2003/02
ASAHI KASEI
[AK4358]
Timing Diagram
1/fCLK VIH VIL tCLKH tCLKL
dCLK=tCLKH x fCLK, tCLKL x fCLK
MCLK
1/fs VIH VIL
LRCK
tBCK VIH VIL tBCKH tBCKL
BICK
Clock Timing
LRCK tBLR tLRB
VIH VIL
BICK tSDS tSDH
VIH VIL
SDTI
VIH VIL
Audio Serial Interface Timing (PCM Mode)
MS0203-E-00 - 10 -
2003/02
ASAHI KASEI
[AK4358]
tDCK tDCKL tDCKH VIH VIL tDDD DSDL DSDR VIH VIL
DCLK
Audio Serial Interface Timing (DSD Normal Mode, DCKB = "0")
tDCK tDCKL tDCKH VIH VIL tDDD DSDL DSDR tDDD VIH VIL
DCLK
Audio Serial Interface Timing (DSD Phase Modulation Mode, DCKB = "0")
VIH CSN VIL tCSS tCCKL tCCKH VIH VIL tCDS tCDH VIH VIL
CCLK
CDTI
C1
C0
R/W
A4
WRITE Command Input Timing
MS0203-E-00 - 11 -
2003/02
ASAHI KASEI
[AK4358]
tCSW VIH CSN VIL tCSH CCLK VIH VIL
CDTI
D3
D2
D1
D0
VIH VIL
WRITE Data Input Timing
VIH SDA VIL tBUF tLOW tR tHIGH tF tSP VIH SCL VIL tHD:STA Stop Start tHD:DAT tSU:DAT tSU:STA Start tSU:STO Stop
I2C Bus mode Timing
tPD
PDN
VIL
Power-down Timing
MS0203-E-00 - 12 -
2003/02
ASAHI KASEI
[AK4358]
OPERATION OVERVIEW D/A Conversion Mode
The AK4358 can perform D/A conversion for both PCM data and DSD data. When DSD mode, DSD data can be input from DCLK, DSDL1-4 and DSDR1-4 pins. When PCM mode, PCM data can be input from BICK, SDTI1-4 and LRCK pins. PCM/DSD mode changes by D/P bit. When PCM/DSD mode changes by D/P bit, the AK4358 should be reset by RSTN bit, PW bit (PW1=PW2=PW3=PW4= "0") or PDN pin. It takes about 2/fs to 3/fs to change the mode. D/P bit 0 1 DAC Output PCM DSD
Table 1. DSD/PCM Mode Control
System Clock
1) PCM Mode The external clocks, which are required to operate the AK4358, are MCLK, LRCK and BICK. The master clock (MCLK) should be synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation filter and the delta-sigma modulator. There are two methods to set MCLK frequency. In Manual Setting Mode (ACKS = "0": Register 00H), the sampling speed is set by DFS0/1(Table 2). The frequency of MCLK at each sampling speed is set automatically. (Table 3~Table 5). In Auto Setting Mode (ACKS = "1": Default), as MCLK frequency is detected automatically (Table 6), and the internal master clock becomes the appropriate frequency (Table 7), it is not necessary to set DFS0/1. When ACKSN = "H", regardless of ACKS bit setting the AK4358 operates by Manual Setting Mode. When ACKSN = "L", ACKS bit setting is valid. All external clocks (MCLK, BICK and LRCK) should always be present whenever the AK4358 is in the normal operation mode (PDN= "H"). If these clocks are not provided, the AK4358 may draw excess current and may fall into unpredictable operation. This is because the device utilizes dynamic refreshed logic internally. The AK4358 should be reset by PDN = "L" after threse clocks are provided. If the external clocks are not present, the AK4358 should be in the power-down mode (PDN= "L"). After exiting reset(PDN = "") at power-up etc., the AK4358 is in the power-down mode until MCLK is input. DSD interface signals (DCLK, DSDL1-4, DSDR1-4) are fixed to "H" or "L". DFS1 0 0 1 DFS0 0 1 0 Sampling Rate (fs) Normal Speed Mode Double Speed Mode Quad Speed Mode 8kHz~48kHz 60kHz~96kHz 120kHz~192kHz Default
Table 2. Sampling Speed (Manual Setting Mode) LRCK fs 32.0kHz 44.1kHz 48.0kHz MCLK 384fs 512fs 12.2880MHz 16.3840MHz 16.9344MHz 22.5792MHz 18.4320MHz 24.5760MHz BICK 64fs 2.0480MHz 2.8224MHz 3.0720MHz
256fs 8.1920MHz 11.2896MHz 12.2880MHz
768fs 24.5760MHz 33.8688MHz 36.8640MHz
Table 3. System Clock Example (Normal Speed Mode @Manual Setting Mode)
MS0203-E-00 - 13 -
2003/02
ASAHI KASEI
[AK4358]
LRCK fs 88.2kHz 96.0kHz
128fs 11.2896MHz 12.2880MHz
MCLK 192fs 256fs 16.9344MHz 22.5792MHz 18.4320MHz 24.5760MHz
384fs 33.8688MHz 36.8640MHz
BICK 64fs 5.6448MHz 6.1440MHz
Table 4. System Clock Example (Double Speed Mode @Manual Setting Mode)
LRCK fs 176.4kHz 192.0kHz
MCLK 128fs 192fs 22.5792MHz 33.8688MHz 24.5760MHz 36.8640MHz
BICK 64fs 11.2896MHz 12.2880MHz
Table 5. System Clock Example (Quad Speed Mode @Manual Setting Mode)
MCLK 512fs 768fs 256fs 384fs 128fs 192fs
Sampling Speed Normal Double Quad
Table 6. Sampling Speed (Auto Setting Mode)
LRCK fs 32.0kHz 44.1kHz 48.0kHz 88.2kHz 96.0kHz 176.4kHz 192.0kHz
128fs 22.5792 24.5760
192fs 33.8688 36.8640
MCLK (MHz) 256fs 384fs 22.5792 33.8688 24.5760 36.8640 -
512fs 16.3840 22.5792 24.5760 -
768fs 24.5760 33.8688 36.8640 -
Sampling Speed Normal Double Quad
Table 7. System Clock Example (Auto Setting Mode) ACKSN pin ACKS bit Clock Mode 0 0 Manual Setting Mode 0 1 Auto Setting Mode (Default) 1 0 Manual Setting Mode 1 1 Manual Setting Mode Table 8. Relationship between ACKSN pin and ACKS bit
2) DSD Mode The external clocks, which are required to operate the AK4358, are MCLK and DCLK. The master clock (MCLK) should be synchronized with DSD clock (DCLK) but the phase is not critical. The frequency of MCLK is set by DCKS bit. All external clocks (MCLK, DCLK) should always be present whenever the AK4358 is in the normal operation mode (PDN= "H"). If these clocks are not provided, the AK4358 may draw excess current because the device utilizes dynamic refreshed logic internally. The AK4358 should be reset by PDN= "L" after threse clocks are provided. If the external clocks are not present, the AK4358 should be in the power-down mode (PDN= "L"). After exiting reset(PDN = "") at power-up etc., the AK4358 is in the power-down mode until MCLK is input. PCM interface signals (BICK, LRCK, SDTI1-4) are fixed to "H" or "L".
MS0203-E-00 - 14 -
2003/02
ASAHI KASEI
[AK4358]
DCKS MCLK DCLK
0 512fs 64fs
1 768fs 64fs
Table 9. System Clock (fs=44.1kHz)
Audio Serial Interface Format
1) PCM Mode When PCM mode, data is shifted in via the SDTI1-4 pins using BICK and LRCK inputs. The DIF0-2 as shown in Table 10 can select five serial data modes. Initial value of DIF0-2 bits is "010" and DIF0 bit is ORed with DIF0 pin. In all modes the serial data is MSB-first, 2's compliment format and is latched on the rising edge of BICK. Mode 2 can be used for 16/20 MSB justified formats by zeroing the unused LSBs. When TDM0 = "1", the audio interface becomes TDM mode. In TDM256 mode (TDM1 = "0", Table 11), the serial data of all DAC (eight channels) is input to the SDTI1 pin. The input data to SDTI2-4 pins is ignored. BICK should be fixed to 256fs. "H" time and "L" time of LRCK should be 1/256fs at least. The serial data is MSB-first, 2's compliment format. The input data to SDTI1 pin is latched on the rising edge of BICK. In TDM128 mode (TDM1 = "1", Table 12), the serial data of DAC (four channels; L1, R1, L2, R2) is input to the SDTI1 pin. Other four data (L3, R3, L4, R4) is input to the SDTI2. The input data to SDTI3-4 pins is ignored. BICK should be fixed to 128fs.
Mode 0 1 2 3 4
TDM1 0 0 0 0 0
TDM0 0 0 0 0 0
DIF2 0 0 0 0 1
DIF1 0 0 1 1 0
DIF0 0 1 0 1 0
SDTI Format 16bit LSB Justified 20bit LSB Justified 24bit MSB Justified 24bit I2S Compatible 24bit LSB Justified
LRCK H/L H/L H/L L/H H/L
BICK 32fs 40fs 48fs 48fs 48fs
Figure Figure 1 Figure 2 Figure 3 Figure 4 Figure 2
Default
Table 10. Audio Data Formats (Normal mode)
LRCK
0 1 10 11 12 13 14 15 0 1 10 11 12 13 14 15 0 1
BICK (32fs) SDTI Mode 0
0
15
1
14
6
14
5
15
4
16
3
17
2
1
31
0
0
15
1
14
6
14
5
15
4
16
3
17
2
1
31
0
15
0
14
1
BICK (64fs) SDTI Mode 0
Don't care 15:MSB, 0:LSB 15 14 0 Don't care 15 14 0
Lch Data
Figure 1. Mode 0 Timing
Rch Data
MS0203-E-00 - 15 -
2003/02
ASAHI KASEI
[AK4358]
LRCK
0 1 8 9 10 11 12 31 0 1 8 9 10 11 12 31 0 1
BICK (64fs) SDTI Mode 1 SDTI Mode 4
Don't care 19:MSB, 0:LSB Don't care 23 22 21 20 19 0 Don't care 23 22 21 20 19 0 19 0 Don't care 19 0
23:MSB, 0:LSB
Lch Data
Figure 2. Mode 1,4 Timing
Rch Data
LRCK
0 1 2 22 23 24 30 31 0 1 2 22 23 24 30 31 0 1
BICK (64fs) SDTI
23 22 23:MSB, 0:LSB 1 0 Don't care 23 22 1 0 Don't care 23 22
Lch Data
Figure 3. Mode 2 Timing
Rch Data
LRCK
0 1 2 3 23 24 25 31 0 1 2 3 23 24 25 31 0 1
BICK (64fs) SDTI
23 22 23:MSB, 0:LSB 1 0 Don't care 23 22 1 0 Don't care 23
Lch Data
Figure 4. Mode 3 Timing
Rch Data
MS0203-E-00 - 16 -
2003/02
ASAHI KASEI
[AK4358]
Mode
5 6 7
TDM1 0 0 0 0 0
TDM0 1 1 1 1 1
DIF2 0 0 0 0 1
DIF1 0 0 1 1 0
DIF0 0 1 0 1 0
SDTI Format N/A N/A 24bit MSB Justified 24bit I2S Compatible 24bit LSB Justified
LRCK
BICK
Figure

256fs 256fs 256fs
Figure 5 Figure 6 Figure 7
Table 11. Audio Data Formats (TDM256 mode)
256 BICK
LRCK BICK(256fs) SDTI1(i)
23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22
L1
32 BICK
R1
32 BICK
L2
32 BICK
R2
32 BICK
L3
32 BICK
R3
32 BICK
L4
32 BICK
R4
32 BICK
Figure 5. Mode 5 Timing
256 BICK
LRCK BICK(256fs) SDTI1(i)
23 0 23 0 23 0 23 0 23 0 23 0 23 0 23 0 23
L1
32 BICK
R1
32 BICK
L2
32 BICK
R2
32 BICK
L3
32 BICK
R3
32 BICK
L4
32 BICK
R4
32 BICK
Figure 6. Mode 6 Timing
256 BICK
LRCK BICK(256fs) SDTI1(i)
23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23
L1
32 BICK
R1
32 BICK
L2
32 BICK
R2
32 BICK
L3
32 BICK
R3
32 BICK
L4
32 BICK
R4
32 BICK
Figure 7. Mode 7 Timing
MS0203-E-00 - 17 -
2003/02
ASAHI KASEI
[AK4358]
Mode
8 9 10
TDM1 1 1 1 1 1
TDM0 1 1 1 1 1
DIF2 0 0 0 0 1
DIF1 0 0 1 1 0
DIF0 0 1 0 1 0
SDTI Format N/A N/A 24bit MSB Justified 24bit I2S Compatible 24bit LSB Justified
LRCK
BICK
Figure

128fs 128fs 128fs
Figure 8 Figure 9 Figure 10
Table 12. Audio Data Formats (TDM128 mode)
128 BICK
LRCK BICK(128fs) SDTI1(i)
23 22 0 23 22 0 23 22 0 23 22 0 23 22
L1
32 BICK
R1
32 BICK
0 23 22 0 23 22
L2
32 BICK
0 23 22
R2
32 BICK
0 23 22
SDTI2(i)
23 22
L3
32 BICK
R3
32 BICK
L4
32 BICK
R4
32 BICK
Figure 8. Mode 8 Timing
128 BICK
LRCK BICK(128fs) SDTI1(i)
23 22 0 23 22 0 23 22 0 23 22 0 23
L1
32 BICK
R1
32 BICK
0 23 22 0 23 22
L2
32 BICK
0 23 22
R2
32 BICK
0 23
SDTI2(i)
23 22
L3
32 BICK
R3
32 BICK
L4
32 BICK
R4
32 BICK
Figure 9. Mode 9 Timing
128 BICK
LRCK BICK(128fs) SDTI1(i)
23 22 0 23 22 0 23 22 0 23 22 0 19
L1
32 BICK
R1
32 BICK
0 23 22 0 23 22
L2
32 BICK
0 23 22
R2
32 BICK
0 19
SDTI2(i)
23 22
L3
32 BICK
R3
32 BICK
L4
32 BICK
R4
32 BICK
Figure 10. Mode 10 Timing
MS0203-E-00 - 18 -
2003/02
ASAHI KASEI
[AK4358]
2) DSD Mode In case of DSD mode, DIF0-2 is ignored. The frequency of DCLK is fixed to 64fs. DCKB bit can invert the polarity of DCLK.
DCLK (64fs) DCKB=1 DCLK (64fs) DCKB=0 DSDL,DSDR Normal DSDL,DSDR
Phase Modulation
D0 D0 D1 D2 D3
D1
D1
D2
D2
D3
Figure 11. DSD Mode Timing
D/A conversion mode switching timing
RSTN bit
4/fs
D/A Mode
PCM Mode 0
DSD Mode
D/A Data
PCM Data
DSD Data
Figure 12. D/A Mode Switching Timing (PCM to DSD)
RSTN bit D/A Mode
DSD Mode 4/fs
PCM Mode
D/A Data
DSD Data
PCM Data
Figure 13. D/A Mode Switching Mode Timing (DSD to PCM)
Caution: In DSD mode, the signal level is ranging from 25% to 75%. Peak levels of DSD signal above this duty are not recommended by SACD format book (Scarlet Book).
MS0203-E-00 - 19 -
2003/02
ASAHI KASEI
[AK4358]
De-emphasis Filter
A digital de-emphasis filter is available for 32, 44.1 or 48kHz sampling rates (tc = 50/15s) and is enabled or disabled with DEM0 and DEM1. In case of double speed and quad speed mode, the digital de-emphasis filter is always off. When DSD mode, DEM0-1 is invalid. DEM1 0 0 1 1 DEM0 0 1 0 1 Mode 44.1kHz OFF 48kHz 32kHz Default
Table 13. De-emphasis Filter Control (Normal Speed Mode)
Output Volume
The AK4358 includes channel independent digital output volumes (ATT) with 128 levels at 0.5dB steps including SMUTE. These volumes are in front of the DAC and can attenuate the input data from 0dB to -63dB and mute. Transition time is set by AST1-0 bits(Table 15) When changing levels, transitions are executed via soft changes; thus no switching noise occurs during these transitions. When ATTE bit is set to "0", the DAC input data goes to "0" immediately. It takes a time of group delay to mute the analog output. ATTE bit should be "1" to enable the volume setting. ATTE ATT6-0 7FH 7EH 7DH : 02H 01H 00H Don't care Attenuation Level 0dB -0.5dB -1.0dB : -62.5dB -63.0dB SMUTE (-) OFF ( "0" )
Default
1
0
Table 14. Attenuation Level of Output Volume Mode 0 1 2 3 ATS1 0 0 1 1 ATS0 0 1 0 1 ATT speed 1792/fs 896/fs 256/fs N/A
Default
Table 15. Transition time of output volume In case of Mode 0, it takes 1792/fs to transit from 7FH(0dB) to 00H(SMUTE). In case Mode1, it takes 896/fs to transit from 7FH(0dB) to 00H(SMUTE). In case Mode2 and 3,it takes 256/fs to transit from 7FH(0dB) to 00H (SMUTE). If PDN pin goes to "L", ATT6-0 registers are initialized to 7FH.ATT6-0 registers go to 7FH when RSTN bit is set to "0". When RSTN bit returns to "1", ATT6-0 registers go to the set value. Digital output volume function is independent of soft mute function. The setting value of the register is held when switching between PCM mode and DSD mode.
MS0203-E-00 - 20 -
2003/02
ASAHI KASEI
[AK4358]
Zero Detection
When the input data at all channels are continuously zeros for 8192 LRCK cycles, the AK4358 has Zero Detection like Table 16. DZF pin immediately goes to "L" if input data of each channel is not zero after going DZF "H". If RSTN bit is "0", DZF pin goes to "H". DZF pin goes to "L" at 4~5LRCK if input data of each channel is not zero after RSTN bit returns to "1". Zero detect function can be disabled by DZFE bit. In this case, all DZF pins are always "L". When one of PW1-4 bit is set to "0", the input data of DAC that the PW bit is set to "0" should be zero in order to enable zero detection of the other channels. When all PW1-4 bits are set to "0", DZF pin fixes "L". DZFB bit can invert the polarity of DZF pin. DZF Pin DZF1 DZF2 DZF3 Operations ANDed output of zero detection flag of each channel set to "1" in 0DH register ANDed output of zero detection flag of each channel set to "1" in 0EH register ANDed output of zero detection flag of each channel set to "1" in 0FH register Table 16. DZF pins Operation
Soft Mute Operation
Soft mute operation is performed at digital domain. When the SMUTE bit goes to "1", the output signal is attenuated by - during ATT_DATAxATT transition time (Table 15) from the current ATT level. When the SMUTE bit is returned to "0", the mute is cancelled and the output attenuation gradually changes to the ATT level during ATT_DATAxATT transition time. If the soft mute is cancelled before attenuating to - after starting the operation, the attenuation is discontinued and returned to ATT level by the same cycle. The soft mute is effective for changing the signal source without stopping the signal transmission.
SMUTE bit (1) (1) (3)
ATT Level Attenuation
-
GD (2) AOUT (4) 8192/fs GD
DZF pin
Notes: (1) ATT_DATAxATT transition time (Table 15). For example, in Normal Speed Mode, this time is 1792LRCK cycles (1792/fs) at ATT_DATA=128. (2) The analog output corresponding to the digital input has a group delay, GD. (3) If the soft mute is cancelled before attenuating to - after starting the operation, the attenuation is discontinued and returned to ATT level by the same cycle. (4) When the input data at each channel is continuously zeros for 8192 LRCK cycles, DZF pin of each channel goes to "H". DZF pin immediately goes to "L" if input data are not zero after going DZF "H". Figure 14. Soft Mute and Zero Detection
MS0203-E-00 - 21 -
2003/02
ASAHI KASEI
[AK4358]
System Reset
The AK4358 should be reset once by bringing PDN= "L" upon power-up. The analog section exits power-down mode by MCLK input and then the digital section exits power-down mode after the internal counter counts MCLK during 4/fs.
Power-down
The AK4358 is placed in the power-down mode by bringing PDN pin "L" and the anlog outputs are floating (Hi-Z). Figure 6 shows an example of the system timing at the power-down and power-up. Each DAC can be powered down by each power-down bit (PW1-3) "0". In this case, the internal register values are not initialized and the analog output is Hi-Z. Because some click noise occurs, the analog output should be muted externally if the click noise influences system application.
PDN
Internal State D/A In (Digital)
GD
Normal Operation
Power-down
Normal Operation
"0" data
(1)
GD
D/A Out (Analog)
Clock In
MCLK, LRCK, BICK
(3) (4)
(2)
(3)
(1)
Don't care
DZF External MUTE
(6)
(5)
Mute ON
Notes: (1) The analog output corresponding to digital input has the group delay (GD). (2) Analog outputs are floating (Hi -Z) at the power-down mode. (3) Click noise occurs at the edge of PDN signal. This noise is output even if "0" data is input. (4) The external clocks (MCLK, BICK and LRCK) can be stopped in the power-down mode (PDN = "L"). (5) Please mute the analog output externally if the click noise (3) influence system application. The timing example is shown in this figure. (6) DZF pins are "L" in the power-down mode (PDN = "L"). Figure 15. Power-down/up Sequence Example
MS0203-E-00 - 22 -
2003/02
ASAHI KASEI
[AK4358]
Reset Function
When RSTN=0, DAC is powered down but the internal register values are not initialized. The analog outputs go to VCOM voltage and DZFL/DZFR pins go to "H". Figure 16 shows the example of reset by RSTN bit.
RSTN bit
3~4/fs (6) 2~3/fs (6)
Internal RSTN bit Internal State D/A In (Digital) (1) D/A Out (Analog)
Clock In
MCLK,LRCK,BICK
Normal Operation
Digital Block Power-down
Normal Operation
"0" data GD GD
(3)
(2) (4)
Don't care
(3)
(1)
2/fs(5)
DZF
Notes: (1) The analog output corresponding to digital input has the group delay (GD). (2) Analog outputs go to VCOM voltage. (3) Click noise occurs at the edges(" ") of the internal timing of RSTN bit. This noise is output even if "0" data is input. (4) The external clocks (MCLK, BICK and LRCK) can be stopped in the reset mode (RSTN = "L"). (5) DZF pins go to "H" when the RSTN bit becomes "0", and go to "L" at 2/fs after RSTN bit becomes "1". (6) There is a delay, 3~4/fs from RSTN bit "0" to the internal RSTN bit "0", and 2~3/fs from RSTN bit "1" to the internal RSTN "1". Figure 16. Reset Sequence Example
MS0203-E-00 - 23 -
2003/02
ASAHI KASEI
[AK4358]
Register Control Interface
The AK4358 controls its functions via registers. 2 types of control mode write internal registers. In the I2C-bus mode, the chip address is determined by the state of the CAD0 and CAD1 inputs. In 3-wire mode, the CAD1 input is fixed to "1" and Chip Address C0 is determined by the state of the CAD0 pin. PDN = "L" initializes the registers to their default values. Writing "0" to the RSTN bit resets the internal timing circuit, but the register data is not initialized. * The AK4358 does not support the read command. * When the AK4358 is in the power down mode (PDN = "L") or the MCLK is not provided, Writing to control register is invalid.
Function Manual Setting Mode De-emphasis DZFE SMUTE Audio data format DSD mode Attenuator Slow roll-off response
Pin set-up O X X X DIF0 X X X
Register set-up O O O O O O O O
Table 17. Function Table (O: Supported, X: Not supported)
(1) 3-wire Serial Control Mode (I2C = "L") 3-wire P interface pins, CSN, CCLK and CDTI, write internal registers. The data on this interface consists of Chip Address (2bits, C1/0; C1 is fixed to "1" and C0=CAD0), Read/Write (1bit; fixed to "1", Write only), Register Address (MSB first, 5bits) and Control Data (MSB first, 8bits). The AK4358 latches the data on the rising edge of CCLK, so data should clocked in on the falling edge. The writing of data becomes valid by the rising edge of CSN. The clock speed of CCLK is 5MHz (max).
CSN
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CCLK
CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
C1-C0: R/W: A4-A0: D7-D0:
Chip Address (C1= "1", C0=CAD0) READ/WRITE (Fixed to "1", Write only) Register Address Control Data
Figure 17. Control I/F Timing
MS0203-E-00 - 24 -
2003/02
ASAHI KASEI (2) I2C-bus Control Mode (I2C= "H")
[AK4358]
The AK4358 supports the standard-mode I2C-bus (max:100kHz). Then the AK4358 does not support a fast-mode I2C-bus system (max: 400kHz). Figure 18 shows the data transfer sequence at the I2C-bus mode. All commands are preceded by a START condition. A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition (Figure 22). After the START condition, a slave address is sent. This address is 7 bits long followed by an eighth bit which is a data direction bit (R/W) (Figure 19). The most significant five bits of the slave address are fixed as "00100". The next two bits are CAD1 and CAD0 (device address bits). These two bits identify the specific device on the bus. The hard-wired input pins (CAD1 pin and CAD0 pin) set them. If the slave address match that of the AK4358 and R/W bit is "0", the AK4358 generates the acknowledge and the write operation is executed. If R/W bit is "1", the AK4358 generates the not acknowledge since the AK4358 can be only a slave-receiver. The master must generate the acknowledge-related clock pulse and release the SDA line (HIGH) during the acknowledge clock pulse (Figure 23). The second byte consists of the address for control registers of the AK4358. The format is MSB first, and those most significant 3-bits are fixed to zeros (Figure 20). Those data after the second byte contain control data. The format is MSB first, 8bits (Figure 21). The AK4358 generates an acknowledge after each byte has been received. A data transfer is always terminated by a STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition (Figure 22). The AK4358 is capable of more than one byte write operation by one sequence. After receipt of the third byte, the AK4358 generates an acknowledge, and awaits the next data again. The master can transmit more than one byte instead of terminating the write cycle after the first data byte is transferred. After the receipt of each data, the internal 5bits address counter is incremented by one, and the next data is taken into next address automatically. If the addresses exceed 1FH prior to generating the stop condition, the address counter will "roll over" to 00H and the previous data will be overwritten. The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW (Figure 24) except for the START and the STOP condition.
S T A R T S T O P Sub Address(n) A C K A C K Data(n) A C K Data(n+1) A C K A C K Data(n+x) A C K P
R/W
SDA
S
Slave Address
Figure 18. Data transfer sequence at the I2C-bus mode
0
0
1
0
0
CAD1
CAD0
R/W
(Those CAD1/0 should match with CAD1/0 pins) Figure 19. The first byte
0
0
0
A4
A3
A2
A1
A0
Figure 20. The second byte
D7
D6
D5
D4
D3
D2
D1
D0
Figure 21. Byte structure after the second byte
MS0203-E-00 - 25 -
2003/02
ASAHI KASEI
[AK4358]
SDA
SCL S start condition P stop condition
Figure 22. START and STOP conditions
DATA OUTPUT BY MASTER not acknowledge DATA OUTPUT BY SLAVE(AK4529) acknowledge SCL FROM MASTER S clock pulse for acknowledgement
1
2
8
9
START CONDITION
Figure 23. Acknowledge on the I2C-bus
SDA
SCL
data line stable; data valid
change of data allowed
Figure 24. Bit transfer on the I2C-bus
MS0203-E-00 - 26 -
2003/02
ASAHI KASEI
[AK4358]
Register Map
Addr 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH Register Name Control 1 Control 2
Speed & Power Down Control
De-emphasis Control LOUT1 ATT Control ROUT1 ATT Control LOUT2 ATT Control ROUT2 ATT Control LOUT3 ATT Control ROUT3 ATT Control Control 3 LOUT4 ATT Control ROUT4 ATT Control DZF1 Control DZF2 Control DZF3 Control
D7 ACKS 0 0 0 ATTE ATTE ATTE ATTE ATTE ATTE TDM1 ATTE ATTE L1 L1 L1
D6 SLOW 0 PW4 0 ATT6 ATT6 ATT6 ATT6 ATT6 ATT6 TDM0 ATT6 ATT6 R1 R1 R1
D5 0 0 DFS1
0
D4 DZFE 0 DFS0
0
D3 DIF2 0 PW3
0
D2 DIF1 0 PW2
0
D1 DIF0
SMUTE
PW1
DEM1
D0 RSTN RSTN RSTN
DEM0
ATT5 ATT5 ATT5 ATT5 ATT5 ATT5 DCKS ATT5 ATT5 L2 L2 L2
ATT4 ATT4 ATT4 ATT4 ATT4 ATT4 D/P ATT4 ATT4 R2 R2 R2
ATT3 ATT3 ATT3 ATT3 ATT3 ATT3 DCKB ATT3 ATT3 L3 L3 L3
ATT2 ATT2 ATT2 ATT2 ATT2 ATT2 DZFB ATT2 ATT2 R3 R3 R3
ATT1 ATT1 ATT1 ATT1 ATT1 ATT1 ATS1 ATT1 ATT1 L4 L4 L4
ATT0 ATT0 ATT0 ATT0 ATT0 ATT0 ATS0 ATT0 ATT0 R4 R4 R4
Note: For addresses from 10H to 1FH, data must not be written. When PDN goes to "L", the registers are initialized to their default values. When RSTN bit goes to "0", the only internal timing is reset, and the registers are not initialized to their default values. All data can be written to the registers even if PW1-4 or RSTN bit is "0". ACKS bit is ANDed with the ACKSN pin. DIF0 bit is ORed with the DIF pin.
MS0203-E-00 - 27 -
2003/02
ASAHI KASEI
[AK4358]
Register Definitions
Addr 00H Register Name Control 1 Default D7 ACKS 1 D6 SLOW 0 D5 0 0 D4 DZFE 1 D3 DIF2 0 D2 DIF1 1 D1 DIF0 0 D0 RSTN 1
RSTN: Internal timing reset 0: Reset. All DZF pins go to "H" and any registers are not initialized. 1: Normal operation When MCLK frequency or DFS changes, the AK4358 should be reset by PDN pin or RSTN bit. DIF2-0: Audio data interface modes (See Table 10, Table 11, Table 12, PCM Only) Initial: "010" Register bit of DIF0 is ORed with the DIF0 pin. DZFE: Data Zero Detect Enable 0: Disable 1: Enable Zero detect function can be disabled by DZFE bit "0". In this case, the DZF pins are "L" at DZFB bit "0" and are "H" at DZFB bit "1". SLOW: Slow Roll-off Filter Enable (PCM Only) 0: Sharp Roll-off Filter 1: Slow Roll-off Filter ACKS: Master Clock Frequency Auto Setting Mode Enable 0: Disable, Manual Setting Mode 1: Enable, Auto Setting Mode Master clock frequency is detected automatically at ACKS bit "1". In this case, the setting of DFS1-0 is ignored. When this bit is "0", DFS1-0 set the sampling speed mode. Register bit of ACKS is ANDed with the inverted of the ACKSN pin.
Addr 01H
Register Name Control 2 Default
D7 0 0
D6 0 0
D5 0 0
D4 0 0
D3 0 0
D2 0 0
D1
SMUT E
D0 RSTN 1
0
RSTN: Internal timing reset 0: Reset. All DZF pins of go to "H" and any registers are not initialized. 1: Normal operation When MCLK frequency or DFS changes, the AK4358 should be reset by PDN pin or RSTN bit. SMUTE: Soft Mute Enable 0: Normal operation 1: All DAC outputs soft-muted
MS0203-E-00 - 28 -
2003/02
ASAHI KASEI
[AK4358]
Addr 02H
Register Name
Speed & Power Down Control
Default
D7 0 0
D6 PW4 1
D5 DFS1 0
D4 DFS0 0
D3 PW3 1
D2 PW2 1
D1 PW1 1
D0 RSTN 1
RSTN: Internal timing reset 0: Reset. All DZF pins go to "H" and any registers are not initialized. 1: Normal operation When MCLK frequency or DFS changes, the AK4358 should be reset by PDN pin or RSTN bit. PW4-1: Power-down control (0: Power-down, 1: Power-up) PW1: Power down control of DAC1 PW2: Power down control of DAC2 PW3: Power down control of DAC3 PW4: Power down control of DAC4 All sections are powered-down by PW1=PW2=PW3=PW4=0. DFS1-0: Sampling speed control (See Table 2, PCM Only) 00: Normal speed 01: Double speed 10: Quad speed When changing between Normal/Double Speed Mode and Quad Speed Mode, some click noise occurs. Addr 03H Register Name De-emphasis Control Default D7 0 0 D6 0 0 D5
0
D4
0
D3
0
D2
0
D1
DEM1
D0
DEM0
0
0
0
0
0
1
DEM1-0: De-emphasis response control for DAC1/2/3/4 data on SDTI1/2/3/4 (See Table 13, PCM only) Initial: "01", OFF Addr 04H 05H 06H 07H 08H 09H 0BH 0CH Register Name LOUT1 ATT Control ROUT1 ATT Control LOUT2 ATT Control ROUT2 ATT Control LOUT3 ATT Control ROUT3 ATT Control LOUT4 ATT Control ROUT4 ATT Control Default D7 ATTE ATTE ATTE ATTE ATTE ATTE ATTE ATTE 1 D6 ATT6 ATT6 ATT6 ATT6 ATT6 ATT6 ATT6 ATT6 1 D5 ATT5 ATT5 ATT5 ATT5 ATT5 ATT5 ATT5 ATT5 1 D4 ATT4 ATT4 ATT4 ATT4 ATT4 ATT4 ATT4 ATT4 1 D3 ATT3 ATT3 ATT3 ATT3 ATT3 ATT3 ATT3 ATT3 1 D2 ATT2 ATT2 ATT2 ATT2 ATT2 ATT2 ATT2 ATT2 1 D1 ATT1 ATT1 ATT1 ATT1 ATT1 ATT1 ATT1 ATT1 1 D0 ATT0 ATT0 ATT0 ATT0 ATT0 ATT0 ATT0 ATT0 1
ATT6-0: Attenuation Level 128 levels, 0.5dB step (See Table 14) ATTE: Attenuation Output Enable 0: Disable 1: Enable
MS0203-E-00 - 29 -
2003/02
ASAHI KASEI
[AK4358]
Addr 0AH
Register Name Control 3 Default
D7 TDM1 0
D6 TDM0 0
D5 DCKS 0
D4 D/P 0
D3 DCKB 0
D2 DZFB 0
D1 ATS1 0
D0 ATS0 0
ATS1-0: DATT Speed Setting (See Table 15) Initial: "00", mode 0 DZFB: Inverting Enable of DZF 0: DZF goes "H" at Zero Detection 1: DZF goes "L" at Zero Detection DCKB: Polarity of DCLK (DSD Only) 0: DSD data is output from DCLK falling edge 1: DSD data is output from DCLK rising edge D/P: DSD/PCM Mode Select 0: PCM Mode. SCLK, SDTI1-4, LRCK 1: DSD Mode. DCLK, DSDL1-4, DSDR1-4 When D/P changes form "1" to "0", the AK4358 should be reset by PDN pin, PW bit or RSTN bit. When D/P changes form "0" to "1", the AK4358 should be reset by PW bit or RSTN bit. DCKS: Master Clock Frequency Select at DSD mode (DSD only) 0: 512fs 1: 768fs TDM0-1: TDM Mode Select (PCM only) Mode Normal TDM256 TDM128 TDM1 0 0 1 TDM0 0 1 1 BICK 32fs 256fs fixed 128fs fixed SDTI 1-4 1 1-2 Sampling Speed Normal, Double, Quad Speed Normal Speed Normal, Double Speed
Addr 0DH
Register Name DZF1 Control Default
D7 L1 1
D6 R1 1
D5 L2 1
D4 R2 1
D3 L3 1
D2 R3 1
D1 L4 1
D0 R4 1
L1-4, R1-4: Zero Detect Flag Enable Bit for DZF1 pin 0: Disable 1: Enable
Addr 0EH 0FH
Register Name DZF2 Control DZF3 Control Default
D7 L1 L1 0
D6 R1 R1 0
D5 L2 L2 0
D4 R2 R2 0
D3 L3 L3 0
D2 R3 R3 0
D1 L4 L4 0
D0 R4 R4 0
L1-4, R1-4: Zero Detect Flag Enable Bit for DZF2,3 pins 0: Disable 1: Enable
MS0203-E-00 - 30 -
2003/02
ASAHI KASEI
[AK4358]
SYSTEM DESIGN
Figure 25 shows the system connection diagram. An evaluation board (AKD4358) is available which demonstrates application circuits, the optimum layout, power supply arrangements and measurement results.
+ 10u
Digital 5V
0.1u
Reset Clock
DVSS 12 DVDD 11 MCLK 10 9 7 6 3 5 4 8 2 1
Gen
DZF1
CAD0
DZF2
CAD1
DZF3
LOUT1+
LOUT1-
BICK
PDN
LPF
ROUT1+
MUTE
L1ch OUT R1ch OUT L2ch OUT R2ch OUT L3ch OUT R3ch OUT L4ch OUT
13 SDTI4 14 SDTI1
48 LPF
MUTE
ROUT1- 47 LOUT2+ 46 LOUT2- 45
DSP
15 SDTI2 16 SDTI3 17 LRCK 18 I2C 19 CCLK/SCL
LPF
MUTE
AK4358
ROUT2+ 44 ROUT2- 43 LOUT3+ 42 LPF
MUTE
uP
20 CDTI/SDA 21 CSN/CAD1 22 DCLK 23 DSDL4
Top View
LOUT3- 41 ROUT3+ 40 ROUT3- 39 LOUT4+ 38 33 ROUT4+
LPF
MUTE
LPF
MUTE
26 DSDR1
28 DSDR2
34 VREFH
29 DSDL3
27 DSDL2
35 AVDD
24
30 DSDR3
32 ROUT4-
DSDR4 DSDL1
LOUT4- 37
LPF
MUTE
DSD Data Controller
31 DIF0
36 AVSS
25
+ 0.1u 10u
Analog 5V
Mode Control
LPF MUTE R4ch OUT
System Ground
Analog Ground
Figure 25. Typical Connection Diagram Notes: - LRCK = fs, BICK = 64fs. - When AOUT drives some capacitive load, some resistor should be added in series between AOUT and capacitive load. - All input pins except pull-down pins should not be left floating.
MS0203-E-00 - 31 -
2003/02
ASAHI KASEI
[AK4358]
Digital Ground
Analog Ground
DVSS 12 DVDD 11 MCLK 10 9 8 7 3 2 LOUT1+ 5 6 4 1 ROUT1+ 48 ROUT1LOUT2+ LOUT247 46 45 ROUT2+ 44 ROUT2LOUT3+ LOUT343 42 41 ROUT3+ 40 ROUT3LOUT4+ 33 ROUT4+ 32 ROUT426 DSDR1 28 DSDR2 30 DSDR3 34 VREFH 27 DSDL2 29 DSDL3
LOUT4-
DZF1
DZF2
CAD1
CAD0
DZF3
13 SDTI4
System Controller
14 SDTI1 15 SDTI2 16 SDTI3 17 LRCK 18 I2C 19 CCLK/SCL 20 CDTI/SDA 21 CSN/CAD1 22 DCLK 23 DSDL4 25 DSDL1 35 AVDD 24 DSDR4 31 DIF0
AK4358
LOUT1-
BICK
PDN
39 38 37
Figure 26. Ground Layout AVSS and DVSS must be connected to the same analog ground plane.
1. Grounding and Power Supply Decoupling
AVDD and DVDD are usually supplied from analog supply in system and should be separated from system digital supply. Alternatively if AVDD and DVDD are supplied separately, the power up sequence is not critical. AVSS and DVSS of the AK4358 must be connected to analog ground plane. System analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitor, especially 0.1F ceramic capacitor for high frequency should be placed as near to AVDD and DVDD as possible.
2. Voltage Reference
VREFH sets the analog output range. VREFH pin is normally connected to AVDD with a 0.1F ceramic capacitor. All signals, especially clocks, should be kept away from the VREFH pin in order to avoid unwanted coupling into the AK4358.
3. Analog Outputs
The analog outputs are full-differential outputs and 0.5 x VREFH Vpp (typ) centered around the internal common voltage (about AVDD/2). The differential outputs are summed externally, VAOUT=(AOUT+)-(AOUT-) between AOUT+ and AOUT-. If the summing gain is 1, the output range is 5.0Vpp (typ @VREFH=5V). The bias voltage of the external summing circuit is supplied externally. The input data format is 2's complement. The output voltage(VAOUT) is a positive full scale for 7FFFFF (@24bit) and a negative full scale for 800000H (@24bit). The ideal VAOUT is 0V for 000000H (@24bit). The internal switched-capacitor filter and external low pass filter attenuate the noise generated by the delta-sigma modulator beyond the audio passband. DC offset on AOUT+/- is eliminated without AC coupling since the analog outputs are differential.
MS0203-E-00 - 32 -
36 AVSS
2003/02
ASAHI KASEI
[AK4358]
4. External Analog Filter
It is recommended by SACD format book (Scarlet Book) that the filter response at SACD playback is an analog low pass filter with a cut-off frequency of maximum 50kHz and a slop of minimum 30dB/Oct. The AK4358 can achieve this filter response by combination of the internal filter (Table 18) and an external filter (Figure 27). Frequency 20kHz 50kHz 100kHz Gain -0.4dB -2.8dB -15.5dB
Table 18. Internal Filter Response at DSD mode
AOUT2.5Vpp
2.0k
1.8k 1.0k 2200p 3300p
4.3k 270p
+Vop
1.8k 1.0k
2.0k
+
AOUT+
2.5Vpp
4.3k 270p
Analog Out
5.65Vpp
-Vop
Figure 27. External 3rd order LPF Circuit Example Frequency Gain 20kHz -0.05dB 50kHz -0.51dB 100kHz -16.8dB DC gain = 1.07dB Table 19. 3rd order LPF (Figure 27) Response
AOUT2.5Vpp
3.9k R1
4.7k 470p
+Vop
3900p 3.9k R1
AOUT+
2.5Vpp
Analog Out
-Vop
6.05Vpp
4.7k
470p
When R1=180 fc=90.1kHz, Q=0.735, g=-0.04dB at 40kHz When R1=150 fc=99.0kHz, Q=0.680, g=-0.23dB at 40kHz
Figure 28. External 2nd order LPF Circuit Example for PCM
MS0203-E-00 - 33 -
2003/02
ASAHI KASEI
[AK4358]
PACKAGE
48pin LQFP(Unit:mm)
9.0 0.2 7.0 36 37 25
1.70Max 0.13 0.13
1.40 0.05 24 9.0 0.2
48 1 0.22 0.08 12
13
7.0
0.16 0.07 0.5 0.10 M
0 10
0.10
0.5 0.2
Package & Lead frame material
Package molding compound: Lead frame material: Lead frame surface treatment: Epoxy Cu Solder (Pb free) plate
MS0203-E-00 - 34 -
2003/02
ASAHI KASEI
[AK4358]
MARKING
AKM
AK4358VQ XXXXXXX
1
1) Asahi Kasei Logo 2) Marking Code: AK4358VQ 3) Date Code: XXXXXXX(7 digits) 4) Pin #1 indication
IMPORTANT NOTICE * These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. * AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. * Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. * AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. * It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification.
MS0203-E-00 - 35 -
2003/02

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